1. Field of the Invention
The present invention relates to an analog PLL (Phase-Locked Loop) circuit for use in a semiconductor integrated circuit chip.
2. Description of the Related Art
Semiconductor integrated circuit chips incorporate a PLL circuit for synchronizing a clock signal supplied to various logic circuits in the integrated circuit with a reference clock signal that is supplied from a source external to the integrated circuit.
FIG. 1 of the accompanying drawings shows a block diagram of a conventional PLL circuit in an integrated circuit chip. As shown in FIG. 1, reference clock signal 53 that is supplied from an external source is supplied to an input terminal of analog PLL circuit 52, and a synchronous clock signal supplied to each of logic circuits 57 in an integrated circuit is supplied as feedback signal 54 to another input terminal of analog PLL circuit 52. Analog PLL circuit 52 controls the phase of output clock signal 55 to eliminate any phase difference between reference clock signal 53 and feedback signal 54.
Output clock signal 55 which has been phase-controlled is supplied as a synchronous clock signal to each of logic circuits 57 through CTS (Clock Tree Synthesis) circuit 56 which has elements arranged and wired in a tree configuration for equalizing delay times of output clock signal 55 at the input terminals of logic circuits 57. The phase of output clock signal 55 which is supplied from analog PLL circuit 52 is controlled such that the phase corresponding to the delay time caused by CTS circuit 56 is subtracted from the phase of output clock signal 55 in advance.
Analog PLL circuit 52 comprises, for example, a phase comparator for comparing the phase of feedback signal 54 as a synchronous clock signal supplied from CTS 56 with the phase of reference clock signal 53, a control voltage generator comprising a low-pass filter for generating a control voltage corresponding to the result of comparison carried out by the phase comparator, and a voltage-controlled oscillator (VCO) whose oscillating frequency is controlled by the control voltage. The design of analog PLL circuit 52 is well known to those skilled in the art, and will not be described in detail below. Japanese Patent Laid-Open Publication No. 111415/01 discloses a technology, described in detail below, for increasing the accuracy of phase synchronization of a PLL circuit in a semiconductor integrated circuit, and preventing decrease of the accuracy of phase comparison due to manufacturing variations and interconnection conditions in the integrated circuit. First and second variable delay elements whose delay times can individually be varied are inserted respectively into a first path which extends from a reference clock input terminal of a semiconductor integrated circuit to an input terminal of a phase comparator of a PLL circuit and a second path which serves as a feedback path to another input terminal of the phase comparator for a clock signal that is supplied from the PLL circuit and output to a logic circuit through a CTS circuit. A delay time difference between a third path and a fourth path which are formed equivalently to the first path and the second path, respectively, is measured, and delay times of the first and second variable delay elements are established based on the measured delay time difference between the third path and the fourth path. In this manner, delay times of the first path and the second path are equalized to each other, thus correcting a phase error which would be produced due to a delay time difference between the first path and the second path.
With the above PLL circuit incorporated, it is possible to synchronize a synchronous clock signal (feedback signal 54) supplied to each of logic circuits 57 connected to CTS circuit 56 with reference clock signal 53 from the external source. Furthermore, as disclosed in Japanese Patent Laid-Open Publication No. 111415/01, the accuracy of phase synchronization can be increased by eliminating a phase error based on the difference between the path of the reference clock signal supplied to the phase comparator and the feedback path of the output clock signal. Actually, however, it is very difficult to make the phase difference between the synchronous clock signal (feedback signal) supplied to each of the logic circuits and the reference signal from the external circuit, smaller than a steady state phase error between the reference clock signal supplied to the phase comparator of the analog PLL circuit and the feedback signal due to a relative error or leakage in the circuitry of the analog PLL circuit.
With the arrangement shown in FIG. 1 or disclosed in Japanese Patent Laid-Open Publication No. 111415/01, therefore, the reference clock signal (reference signal 53) applied to the input terminal of the phase comparator and the synchronous clock signal (feedback signal 54) supplied to each of the logic circuits are not precisely in phase, and the PLL circuit becomes stable while these signals are being kept out of phase. There are limitations on attempts to reduce the steady state phase error due to variations and leakage in the analog PLL circuit, making it difficult to synchronize the synchronous clock signal supplied to each of the logic circuits with the reference clock signal perfectly.
If the frequency of the synchronous clock signal is low, then the steady state phase error does not significantly adversely affect the operation of the PLL circuit insofar as the steady state phase error is within a certain allowable range. However, if the frequency of the synchronous clock signal is high, then the allowable range for the steady state phase error is so tight that the steady state phase error cannot be ignored in the operation of the PLL circuit.
FIG. 2 of the accompanying drawings shows a block diagram of a conventional circuit designed for reducing a steady state phase error. The illustrated conventional circuit has a DLL (Delay Locked Loop) circuit placed in a stage following an analog PLL circuit independently thereof. The DLL circuit serves to reduce a steady state phase error which occurs in the analog PLL circuit for thereby synchronizing a synchronous clock signal supplied to each logic circuit with a reference clock signal supplied from an external source.
In FIG. 2, the phase comparator in analog PLL circuit 61 is supplied with reference clock signal 63 from an external source and feedback signal 65 as an output clock signal from the phase comparator, and supplies output clock signal 65, whose phase difference from reference clock signal 63 is reduced to a value within the range of the steady state phase error, to DLL circuit 62.
DLL circuit 62 has a variable delay circuit comprising a plurality of buffers for delaying output clock signal 65 supplied from analog PLL circuit 61 for at least one period, and a delay time control circuit for being supplied with, and detecting a phase difference between, reference clock signal 63 and synchronous clock signal 68 supplied from CTS circuit 66 and controlling a delay caused by the variable delay circuit according to the detected phase difference.
Specifically, the DLL circuit 62 compares the phase of reference clock signal 63 with the phase of synchronous clock signal 68, and controls the delay caused by the variable delay circuit in order to eliminate the phase difference between reference clock signal 63 and synchronous clock signal 68. DLL circuit 62 supplies output clock signal 64 whose delay has been controlled to CTS circuit 66. Therefore, synchronous clock signal 68 supplied from CTS circuit 66 is synchronized with reference clock signal 63, so that logic circuit 67 is supplied with a synchronous clock signal which is synchronized with the reference clock signal.
Generally, analog PLL circuits are less susceptible to the noise of power supply and easier to design than digital PLL circuits. However, there are limitations on attempts to reduce the steady state phase error due to variations and leakage in the analog PLL circuits, making it difficult to synchronize the clock signal supplied to each of the logic circuits with the reference clock signal perfectly.
According to the circuit shown in FIG. 2, the DLL circuit placed in the stage following the analog PLL circuit independently thereof is capable of solving the problem of the steady state phase error that occurs in the analog PLL circuit shown in FIG. 1 or disclosed in Japanese Patent Laid-Open Publication No. 111415/01. However, if the accuracy of the phase of the output clock signal is to be increased, then the scale of the PLL circuit becomes larger, resulting in an increase in the area and power consumption of the integrated circuit which incorporates the PLL circuit therein.
In addition, the DLL circuit which operates independently suffers a problem in that it accumulates noise from the power supply and provides jitter generated in the DLL circuit. The variable delay circuit of the DLL circuit usually comprises a plurality of cascaded buffers, such as CMOS inverters, each having a unit delay. The CMOS inverters have switching times (unit delay times) that are liable to suffer noise of a digital power supply, which is propagated as jitter.
In addition, the DLL circuit shown in FIG. 2 is required for the variable delay circuit to delay the input signal for at least one period. On the other hand, if the accuracy of synchronization of the synchronous clock signal is to be increased, then the unit delay time of each buffer needs to be reduced. Consequently, if the input signal is to be delayed for one period and at the same time the accuracy of synchronization of the synchronous clock signal is to be increased, then the number of cascaded buffers is increased, and the circuit scale is also increased. For example, if the frequency of the clock signal is 300 MHz, then the clock signal has a period of 3.3 nsec. If the buffers have a unit delay time of 10 ps, then in order for the variable delay circuit to delay the input signal for at least one period, at least 330 buffers are required to be connected in cascade.